In the context of the processing of video image pixels, it often happens that the data to be processed is stored in buffer memories and is then retrieved to undergo successive digital processing. This is particularly the case with time noise reduction, which is used to reduce the recursive time noise in a noisy video signal. FIG. 1 shows a flow chart of such a time noise reduction method.
This algorithm is essentially based on a space interpolation and on a time interpolation of the pixels. A movement detector is used to decide whether space interpolation or time interpolation may be preferred. The end result is obtained by weighting the space and time interpolations according to the detected movement.
In FIG. 1, the prefix Y designates the luminance component and the prefixes U and V designate the chrominance components of a frame, the prefix C designates a current frame, the prefix P designates a preceding frame, the prefix PP designates a frame immediately prior to the preceding frame, the suffix “n” designates a line “n” of a frame, and the suffix “n+1” designates a subsequent line. The luminance components PY and PPY and the chrominance components CU, PPU, CV and PPV of a preceding frame P and of a prior frame PP are presented at the input of a movement detector 1.
More particularly, the luminance component PYn+1 of a subsequent line of a prior frame P, the luminance component PPYn of a line n of a prior frame PP, obtained by way of a delay line, such as 2, and the luminance component PPYn+1 of a subsequent line of a frame PP are presented at the input of the movement detector 1. With reference to the chrominance components U and V, the chrominance components of a line n and of a subsequent line n+1 of a current frame C and of a prior frame PP, that is to say the components CUn, CUn+1, PPUn, PPUn+1, CVn, CVn+1, PPVn and PPVn+1, are also presented at the input of the movement detector 1.
The value of the movement Mn+1, originating from the movement detector 1, and the prior movement values Mn and Mn−1, obtained by way of delay lines, such as 3, are presented at the input of a filter 4 delivering a weighted coefficient TSW. Moreover, the luminance signal CY of a current frame, of a current line n+2 and of prior lines n+1 and n, originating from corresponding delay lines, such as 5, is the subject of space filtering by way of a corresponding filter 6, so as to obtain a luminance value on a sliding window. A delay line 7 makes it possible to have, at the output of the space filtering, components YSpatn+1, and YSpatn on two consecutive lines.
Moreover, the luminance and chrominance values of a current frame C and of a prior frame PP are presented at the input of respective time filters, such as 8. The filtered values of the luminance and chrominance components YTempn, UTempn and VTemppn are presented, with the filtered component YSpatn and with the weighted coefficient TSW, at a mixer stage 9 in order to supply, as an output, luminance and chrominance components Youtn, Uoutn and Voutn weighted according to the detected movement.
As can be understood, such processes are relatively cumbersome to apply. This is also the case with the various digital processes, which may be applied to video signals, such as the luminance and chrominance separation processes, the change of resolution or “rescaling” processes, the de-interlacing processes, the subjective image improvement processes, such as the processes known as LTI/CTI, DC, i.e. the color-management processes.
As described above with respect to the reduction of time recursive noise, the various processes are usually applied over a sliding window, which takes account of a set of adjacent pixels. These processes therefore use iterative computations and usually involve the use of buffer memories to retain the components of the adjacent lines, and even of the preceding frames. Various approaches are typically used to apply processes of the aforementioned type to video digital signals.
First of all, there are purely hardware approaches. Such approaches may be advantageous to the extent that they make it possible to obtain good performance. But it is understandable that the use of hardware methods may make the process inflexible and difficult to change. Moreover, the use of hardware implementations may use low-level coding, such as the coding known as Register Transfer Level (RTL), which are relatively cumbersome to use. Finally, the use of hardware implementations use a wired control logic that may be relatively difficult to design and may be capable of generating errors.
There are, beside the hardware approaches, purely software approaches. Such approaches may be relatively flexible but may also generate prohibitive production costs. Finally there are approaches that include combining the hardware approaches and the software solutions. Such approaches may include providing coprocessors combined by way of a wired architecture. Such coprocessors may be complex, and each may incorporate a control logic using direct memory access (DMA) and have the same disadvantages as those of the purely hardware solutions. They may also be difficult to control. They may also be difficult to model so that, at the design stage, their performance is relatively difficult to predict.